A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard - I-Scover metadata
ARTICLE

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Metadata details

now loading...

Related ARTICLE(s)

now loading...

Related metadata

now loading...

Search by external websites

now loading...

Login 日本語